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  • 4-bit Adder Subtractor
  • Data flow Modeling
Small Heading

//Using conditional operator

module adder_subtractor(carry,sum,a,b,m);
input [3:0]a;
input [3:0]b;
input m;
output [3:0]sum;
output carry;
wire [3:0]sum,carry;
assign {carry,sum}=m?a+~b+1:a+b;
endmodule

//test bench

module adder_subtractor_test();
reg [3:0]a;
reg [3:0]b;
reg m;
wire carry;
wire [3:0]sum;
adder_subtractor a1(carry,sum,a,b,m);
initial begin
     m=1'b0;  //Adder
     a=4'b0000;b=4'b0001;
 #20 a=4'b1000;b=4'b1010;
 #20 a=4'b1011;b=4'b1111;
 #20 a=4'b1111;b=4'b1011;
 #20 m=1'b1;  //Subtractor
     a=4'b0000;b=4'b0001;
 #20 a=4'b1000;b=4'b1010;
 #20 a=4'b1011;b=4'b1111;
 #20 a=4'b1111;b=4'b1011;
end
endmodule

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