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A verilog portal for needs

eriloGcode

Basics

1.General Syntax

2.Variable Declaration

3.Operators

4.Keywords

initial and always

begin and end

case

if-else

assign

5.Module calling

Combinational logic Design

Half-adder

Full-adder

4-bit adder

4-bit adder-subtractor

Magnitude comparator

4X1 Multiplexer (mux)

2X4 Decoder

ALU- arithmatic logic unit

4X2 Encoder

8X3 Priority-encoder

1X4 Demultiplexer (demux)

Sequential logic Design

Flip-flops synchronous and asynchronous

FSM - finite state machine

Counter

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