4 bit adder | verilogcode

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module adder(carry,sum,a,b);
input [3:0]a;
input [3:0]b;
output wire carry,sum;
assign {carry,sum}=a+b;

endmodule

//test bench

module adder_test();
reg [3:0]a;
reg [3:0]b;
wire carry;
wire [3:0]sum;
adder a1(carry,sum,a,b);
initial begin
a=4'b0000;b=4'b0001;
#20 a=4'b1000;b=4'b1010;
#20 a=4'b1011;b=4'b1111;
#20 a=4'b1111;b=4'b1011;
end
endmodule

4-bit Adder

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4-bit Adder