b variable declaration

contents

following data types are oftenly used

input/output :-as the word suggest these are used to declare ports .

example -

output sum,carry;

input x,y;

here sum and carry will act as output port (output of module) and x,y as input port(input to the module)

ports become important while calling module

reg/wire

this is most imp portion in declaring

reg:-

reg elements can be connected to the input port of called module .
reg elements cannot be connected to the output port of a called module
reg elements can be used as outputs within an actual module.
reg elements cannot be used as inputs within an actual module.
reg elements can be assigned values by (=)or (<=)sign when inside always@ block. and within initial block (=) sign is used to assign values (used in test benches)
unlike wire elements, reg elements cannot be used with assign statement.
reg can, be used to create both combinational and sequential logic.

wire:-

wire elements are used to connect input and output ports of a module instantiation together with some other element in your design. like when using logic circuit we connect output of one gate(here called module) to the input of another gate (any other or same module)
wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block.
wire elements must be driven by something, and cannot store a value without being driven by assign statement or by called module (to store its output)
wire elements are used as inputs and outputs within actual module .
wire elements are a stateless way of connecting two peices in a Verilog-based design.
wire elements often used to model combinational logic.

note: no need to learn all point you'll become familiar after you solve module calling problems

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