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module decoder2_4(z,x,y,e);
input e,x,y;    //e->enable pin
output [3:0]z;
wire xb,yb;
not n1(xb,x),n2(yb,y);
and a(z[0],xb,yb,e),a1(z[1],xb,y,e),
        a2(z[2],x,yb,e),a4(z[3],x,y,e);
endmodule

  • 2*4 Decoder with Active high enable

//testbech
module decoder2_4test();
reg e,x,y;
wire [3:0]z;
decoder2_4 d1(z,x,y,e);
initial begin
e=1'b0;
#20 e=1'b1; x=1'b0;  y=1'b0;
#20  x=1'b0;  y=1'b1;
#20  x=1'b1;  y=1'b0;
#20  x=1'b1;  y=1'b1;
End
Endmodule

 

module decoder2_4(z,x,y,e);
input e,x,y;  //e->enable pin
output reg [3:0]z;
always@(x,y,e)
if(e==0) z=0;
else
case({x,y})  //x most significant bit
2'b00:z=1;
2'b01:z=2;
2'b10:z=4;
2'b11:z=8;
endcase
endmodule

  • Gate level Modeling
  • Behavioral Modeling
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