verilog code for full adder with test bench

module full_adder(carry,sum,x,y,z);

input x,y,z;
output wire carry,sum;
assign {carry,sum}=x+y+z;
endmodule

//test bench

module full_adder_test();

reg x,y,z;

wire carry,sum;

initial begin

x=1'b0; y=1'b0; z=1'b0;

#20 x=1'b0; y=1'b0; z=1'b1;

#20 x=1'b0; y=1'b1; z=1'b0;

#20 x=1'b0; y =1'b1; z=1'b1;

end

endmodule

module full_adder(carry,sum,A,B,Cin);

input A,B,Cin;
output carry,sum;

wire s1,c1,c2;

xor x1(s1,A,B);

and a1(c1,A,B);

xor x2(sum,s1,Cin);

and a2(c2,s1,Cin);

or o1(carry,c1,c2);

endmodule

Also see-Full adder by calling half adder

Full adder is a combinational arithmetic logic circuit that adds three numbers and produces a sum bit (S) and carry bit (C) as the output.

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