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  • initial

Initial blocks are non-synthesisable blocks. These are normally used in test benches. Initial blocks cause certain instructions to be performed at the beginning of the simulation, before any other instructions operate. Initial blocks only operate once.

  • always

Always blocks describe things that should repeat indefinitely, or things that should repeat on a given synchronization condition. An always block with no condition is asynchronous:

​

always

begin

         ...

end

​

This block of code will continuously execute regardless of the clock signal of the circuit.

  • always @

The always @  structure is a synchronous condition structure. It takes the form:

​

always @(<condition> <signal>)

​

Where <condition> can be either posedge, negedge, or omitted. The <signal> parameter is the signal to be synchronized against (usually a clock signal).

 

For instance, if we want a particular block of code to execute at the positive edge of every clock pulse, we would write:

​

always @(posedge clk)

 

If we do not put in either posedge or negedge qualifiers, the always block will be triggered at every change (every positive and negative edge of the signal).

For example:

​

always @(clk)

​

will perform at the positive and negative edges of the clock signal.

  • Edge Triggers

The keywords posedge and negedge are edge trigger conditions, and are only used with always blocks.

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