A verilog portal for needs
eriloGcode
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Multiplexer
//Using conditional operator
module mux4_1(y,s,i);
input [1:0]s;
input [3:0]i;
output y;
wire y;
assign y=s[1]?(s[0]?i[3]:i[2]):(s[0]?i[1]:i[0]);
endmodule
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Data flow Modeling
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Behavioral Modeling
//Using If-else
module mux4_1(y,s,i);
input [1:0]s;
input [3:0]i;
output reg y;
always@(s or i)
begin
if({s[1],s[0]}==2'b00) y=i[0];
else
if({s[1],s[0]}==2'b01) y=i[1];
else
if({s[1],s[0]}==2'b10) y=i[2];
else
if({s[1],s[1]}==2'b11) y=i[3];
end
endmodule
//testbench
module mux4_1test();
reg [1:0]s;
reg [3:0]i;
wire y;
mux4_1 m1(y,s,i);
initial begin
s=2'b00; i=4'b0001;
# 20 s=2'b01; i=4'b0010;
# 20 s=2'b10; i=4'b0100;
# 20 s=2'b11; i=4'b1000;
end
endmodule
//Using case statement
module mux4_1(y,s,i);
input [1:0]s;
input [3:0]i;
output reg y;
always@(s or i)
begin
case(s)
2'b00:y=i[0];
2'b01:y=i[1];
2'b10:y=i[2];
2'b11:y=i[3];
endcase
endendmodule
//testbench
module mux4_1test();
reg [1:0]s;
reg [3:0]i;
wire y;
mux4_1 m1(y,s,i);
initial
begin
s=2'b00; i=4'b0001;
# 20 s=2'b01; i=4'b0010;
# 20 s=2'b10; i=4'b0100;
# 20 s=2'b11; i=4'b1000;
end
endmodule