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Half adder is a combinational  arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output.

Half adder
verilog code half adder

module halfadder(a, b, s, c);
input a;
input b;
output wire s;
output wire c;


assign {c,s}=a+b;                                

 

endmodule

  • Gate Level
  • Data Flow

module halfadder(a, b, s, c);
input a;
input b;
output s;
output c;


xor x1(s,a,b);

and a1(c,a,b);                              

 

endmodule

truth table
half adder gate level
data flow

module halfadder_test();

reg a,b;

wire s,c;

​

halfadder h1(a,b,s,c);

 

initial begin

        a=1'b1;  b=1'b1;

#20 a=1'b1;  b=1'b0;

#20  a=1'b0;  b=1'b1;

#20 a=1'b0;  b=1'b0;

end

 

endmodule

​

​

  • Test bench
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