A verilog portal for needs
eriloGcode
General Syntax
module module_name(< port list>);
declaration
logical portion
endmodule
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module is a keyword which is followed by the name of module.
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module_name an identifier that uniquely names the module.By this module name we can call this module in any other module.
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Port list a list of input,and output variables.
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Declaration section describe the type of each variable e.g. reg, wire, output, input etc. used through-out the module
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Logical portion decides working of your module
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endmodule simply denotes the end of module.
Description
Example
module halfadder(a, b, s, c); //here a,b,s,c are variables either output or input
input a;
input b; //all the variables declared with keyword denoting their types
output s; //helping variables(e.g. wire,reg) are also declared here
output c;
xor x1(s,a,b); //syntax of logical part varies as per level of modeling
and a1(c,a,b);
endmodule
}
}
Structure